This invention relates to digital memory cells and memory systems. More particularly, it relates to static-type semiconductor random access memory (RAM) storage cells and systems.
Various forms of static and dynamic semiconductor storage cells are known in the art. Static cells continue to store data for as long as power is applied to them. In contrast, a dynamic storage cell must be periodically refreshed or it loses the data stored in it. Static cells are generally faster, consume less power and have lower error rates, but have the disadvantage of requiring more space on a semiconductor chip.
As is known, semiconductor storage cells rely on the charge on a parasitic cell capacitance to maintain the state of the cell when it is not being accessed. Unfortunately, this charge gradually leaks off and, if the cell is not accessed for a period of time, the cell is likely to lose its logic state. Dynamic cells solve this problem by periodically refreshing the charge on the appropriate parasitic capacitor. This is effective, but it increases the circuit complexity and decreases the cycle time. Static cells, on the other hand, solve the problem by providing additional circuitry in each storage cell for causing a small leakage current to flow through the cell during non-access periods in such a manner as to replenish the loss of charge on the parasitic capacitor. Unfortunately, this additional circuitry requires more space on the semiconductor chip.
Various forms of static and dynamic semiconductor storage cells are described in U.S. Pat. No. 4,796,227 granted to Richard F. Lyon and Richard R. Schediwy on Jan. 3, 1989. The descriptions in this Lyon and Schediwy patent are hereby incorporated into the present patent application by this reference thereto. The cell constructions described by Lyon and Schediwy have various advantages and disadvantages. Nevertheless, there remains room for further improvement, particularly with respect to cell performance.
The present invention provides an improved static semiconductor RAM storage cell with improved performance characteristics and an improved storage system using many such cells. The improvement is partly accomplished by making use of a largely ignored fourth terminal of a field effect transistor, namely, the body or substrate portion of the transistor. This body or substrate portion is sometimes referred to and will be herein referred to as the xe2x80x9cback gatexe2x80x9d terminal. In the present invention, a bias voltage is applied to the back gate terminals of the bit line coupling transistors in a static RAM storage cell for causing a flow of small compensating currents through the coupling transistors when they are in a non-access condition. These small compensating currents are supplied to the storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell.
A bias voltage may also be applied to the normal gate terminals of the bit line coupling transistors for causing additional flow of compensating currents through the coupling transistors when they are in a non-access condition.
Adaptive bias circuits are provided for adaptively adjusting the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance. These changes in leakage rate may be caused by variations in the manufacturing process, changes in supply voltages and chip voltage gradients, and changes in ambient and chip gradient temperatures. For a better understanding of the present invention, together with other and further advantages and features thereof, reference is made to the following description taken in connection with the accompanying drawings, the scope of the invention being pointed out in the appended claims.